1. Introduction
Rate of data throughput of any memory management system is limited by the number of steps of copying data in and from a system memory residing on a data bus which may be on a network of processors. One aspect of this invention implements transmit and receive descriptors that optimize data processing efficiency of a system memory comprising at least two distinct memories. Data having different levels of priority or other characteristic is received from the bus to be stored in the memory or gathered from the memory to be transmitted. The system memory may comprise node and host memories of a local or wide area network.
By way of example, the invention will be taught within the environment of a fiber distributed data interface (FDDI), described in the copending applications identified hereinabove; however as the principles taught herein are more applicable broadly to memory management systems, the invention is not to be limited to the environment described hereinafter.
2. Discussion
In data manipulation systems handling packets of data arranged in frames (a packet, or burst, of data including certain framing, or "housekeeping", bits is defined as a "frame"; data sent in the form of frames is termed "framed data"), there is often a requirement to transfer frames of data between a system at one location and a system at another location on a network. The frames of data may be arranged in queues representing the same or different levels of priority. An interface circuit that resides between a local system and a network, termed a "network controller", administers data flow between the system and network. This includes buffering the data to compensate for timing discrepancies between the system and network, providing any necessary protocol conversion and carrying out "housekeeping" by adding bits to or stripping bits from the data passing through the controller. Various types of network controller architectures are implemented based on the network operating system employed and on other considerations.
For example, in a network of a type described in copending application (1), supra, for "FDDI CONTROLLER HAVING FLEXIBLE BUFFER MANAGEMENT", incorporated herein by reference, there is a network controller comprising a bus master architecture wherein queues of framed data are transferred from buffers established in a system memory to corresponding regions formed by logical FIFOs in an output buffer for transmission to a network. Between the system memory and the output buffer is a physical FIFO having a predetermined storage capacity, e.g., 32 bytes, for storing the framed data temporarily in route to the output buffer. One purpose of the physical FIFO is to provide buffering of data that is required as a result of differences in the clock rates of system and network clocks. In copending application (2) for "Configuration of SRAMs as Logical FIFOs for Transmit and Receive of Packet Data," in response to a request for transmission to the network, upon receipt of a "token" on the network, and assuming that data is available for transmission, data is transferred from the system memory, one packet at a time, to the transmit FIFO, and then from the transmit FIFO to the network while data still is incoming from the network. This enables the FIFO to transmit to the network before a full frame is received. Frames of data thereby transmitted are stored in corresponding queues formed by the logical FIFOs configured in the output buffer.
Data is transferred in order of priority beginning with the highest until no additional data having the same priority is available for transmission or the unexpired token holding time (THT) during receipt of the token has become less than a threshold value for that priority. Details on this protocol are given in copending application (3), supra, for "METHOD OF AND SYSTEM FOR IMPLEMENTING MULTIPLE LEVELS OF ASYNCHRONOUS PRIORITY IN FDDI NETWORKS", incorporated herein by reference.
Following each transfer of framed data from the system memory, through the physical FIFO to the output buffer, a decision is made either to transfer additional data having the same priority to the physical FIFO thereafter to be transferred to the same output buffer queue, or to transfer data having a different priority through the physical FIFO to another output buffer queue if any additional data is available. Copending application (4) for "METHOD OF AND SYSTEM FOR TRANSFERRING MULTIPLE PRIORITY QUEUES INTO MULTIPLE LOGICAL FIFOs USING A SINGLE PHYSICAL FIFO", incorporated herein by reference, describes one means to prevent "locking-up" of the FIFO. Locking-up occurs when the amount of storage remaining available in the logical FIFO containing a particular queue to be written to is less than the storage capacity of the physical FIFO. Under this condition the physical FIFO cannot unload to the logical FIFO in the buffer.
A system of a type to which an aspect of the invention is particularly applicable incorporates not only a host processor but a node processor as well, each having its own associated memory. This architecture is advantageous as the node processor will free the host processor from communications tasks involved in protocol packet transmission. For example, protocol headers may be processed in the node processor memory while data is passed directly to and from the output buffer, and attached later to a packet for transmission. Rate of data throughput is increased by eliminating the necessity to carry out two steps of copying data for each memory transfer.
The copending applications utilize so-called transmit and receive "descriptors" that contain bits if information defining the status, length and address pointer of each of the buffer regions configured in the system memory. For a first-in first-out (FIFO) memory, wherein storage following the last storage position of the FIFO recirculates to the first, the descriptors take the form of a ring. Hence, a descriptor of this type is termed a "descriptor ring". The present invention is directed to efficient buffer management within a system incorporating multiple system memories and wherein frames or packets of data are stored in buffer regions pointed to by multiple descriptor rings.
Descriptor rings in accordance with the invention manage packet or framed data characterized by header as well as data portions. Normally, the header and data portions of the frame cannot be separated from each other conveniently as the two portions would become uncorrelated, or "lose synchronization" with each other among the buffers. Another aspect of the invention optimizes storage of framed data having header and data portions while maintaining synchronization between frames of data and their corresponding headers.
In a network controller of the type described, the receive data path incoming to the system memory through a single physical FIFO memory has a tendency to become blocked under certain circumstances. For example, if the receive descriptor ring is full or a parity error exists, subsequent packets destined for any descriptor ring in the receive path through the FIFO will become blocked. Although the subsequent packets will be stored in receive queues in the output buffer until the blocking cause is removed, the ring will become blocked again as the buffer has a limited storage capacity. A feature of this invention avoids blocking of the receive data path upon a blocked ring and is independent of the amount of buffer memory available to store queues of receive data during a block.